In many ICs there is a need to synchronize events such as the transfer of data between logic elements. For example, many microprocessors latch data and flip-flop devices synchronous to the rising or falling edge of a clock signal. In modern integrated circuits, clock macros are typically utilized to trigger activity in particular blocks of logic.
A clock macro is a well-known circuit structure that buffers and conditions a clock signal coupled to a set of the state elements, usually a small state machine. The clock macro is typically driven by a global clock signal, with individual clock macros being enabled by a separate enable signal line. The enable line allows a clock macro to generate a clock signal for a particular set of logic at a particular time. Normally, the state elements and their associated clock macro circuits are arranged in a pipeline configuration so the data flow proceeds in a synchronous manner through the circuit.
Such a pipelined circuit arrangement is illustrated in FIG. 1, where three separate clock macro circuits (Macro.sub.1-3) are shown driving associated flip-flop state elements (FF.sub.1-3). Data flow proceeds from left to right in the schematic diagram of FIG. 1. Each set of state elements may drive associated machine logic (e.g., combinatorial logic) as indicated by blocks M.sub.1 and M.sub.2 in FIG. 1. Each clock macro functions to generate a single clock pulse cycle responsive to a rising edge of the global clock signal (GCLK) when its enable (EN) input is logically high.
An example of the functionality of the pipelined circuit arrangement of FIG. 1 is provided in the timing diagram of FIG. 2. As can be seen, the Cycle.sub.1 output pulse is generated in response to the first rising edge of the global clock signal when the enable input EN.sub.1 is high. A second Cycle.sub.1 output pulse is also generated responsive to the second rising edge of the GCLK signal since the EN.sub.1 signal is still high when the second GCLK signal arrives. In accordance with pipelined structure of the circuit of FIG. 1, the second clock macro is supposed to output a clock pulse (Cycle.sub.2) one clock cycle after the occurrence of the Cycle.sub.1 output pulse. This is indicated in the timing diagram of FIG. 2 by arrow 11. This requires, of course, that the enable input EN.sub.2 be high when the second GCLK pulse transitions low-to-high.
Continuing down the pipeline, the third clock macro should output a clock pulse (Cycle.sub.3) one clock cycle after the occurrence of the Cycle.sub.2 output pulse when the second GCLK pulse transitions low-to-high and the enable input EN.sub.3 is high. This is indicated in the timing diagram of FIG. 2 by arrow 13. The remaining stages of the pipeline (not shown) operate in a similar manner. Likewise, arrows 12 and 14 in FIG. 2 represent the causal effect of the second Cycle.sub.1 output pulse.
In other words, the correct sequence of events is as follows. Data is first provided to the inputs of FF.sub.1, after which time Clock Macro.sub.1 provides a pulsed clock signal (Cycle.sub.1) to the state elements of FF.sub.1 responsive to the rising edge of GCLK when EN.sub.1 is high. After the outputs of FF.sub.1 pass through some combinatorial logic (M.sub.1) a next set of inputs is provided to FF.sub.2. At the next rising edge of the global clock, EN.sub.2 should be high clock such that Clock Macro.sub.2 generates a pulsed clock signal (Cycle.sub.2), and so on down the pipeline.
Note that the EN.sub.2 and EN.sub.3 signal inputs are not shown in FIG. 2, but would need to be provided to the corresponding clock macros at the same time that the next global clock signal arrives.
One difficulty in the prior art has been how to properly generate and sequence each of the enable input signals to the respective clock macros in the pipelined logic chain. In other words, although the clock macros are connected to the same global clock signal--which gives them proper timing--each clock macro lacks the logical decision whether to generate an output pulse. That logical decision is provided by the enable input signal.
The circuit schematic diagram of FIG. 3 shows one prior art approach to this problem. In FIG. 3, an enable input signal is provided as an input to Clock Macro.sub.1 and also to the data input of flip-flop 30a. Flip-flop 30a is the first in a series of flip-flops 30 that continues for as long as the pipeline extends. The output of flip-flop 30a drives the enable input of the next clock macro in the sequence (i.e., Clock Macro.sub.2) and also the data input of the next enable flip-flop, i.e., 30b. Flip-flops 30 are all clocked synchronously on clock line 29 by inverter 28, which runs off GCLK.
A major disadvantage of the circuit of FIG. 3 is that it consumes a large amount of standby power due to the free running clock signal provided on line 29. In other words, each of the flip-flops 30 operates continuously to provide appropriate enable signals to each of the clock macro stages. As the size of integrated circuits continues to increase, the emphasis on power reduction has never been greater. This means that there is a need to provide alternative circuit solutions that do not consume such large quantities of power.
Another problem with prior art circuits is that the timing constraint on the enable signal comes from flip-flops 30. This places an additional constraint on the enable signal for next-phase staging. In next-phase staging, instead of providing a clock output pulse every global clock cycle, a pulse is provided every phase of the free running clock. This extra constraint requires additional latch circuits (shown as dashed elements 35 in FIG. 3) for proper phase staging. Thus, there exists an unsatisfied need for control circuit that provides proper clock enable staging while overcoming the drawbacks of the prior art.